Computer System Architecture Lab
Computer System Architecture Lab
Home
News
Members
Publications
Research
Gallery
Contact
Light
Dark
Automatic
1
Warped-MC: An Efficient Memory Controller Scheme for Massively Parallel Processors
The performance of GPU’s external memories is becoming more critical since a modern GPU runs thousands of concurrent threads that …
Jonghyun Jeong
,
Myung Kuk Yoon
,
Yunho Oh
,
Gunjae Koo
PDF
Cite
Project
Slides
DOI
Slide Show
CacheRewinder: Revoking Speculative Cache Updates Exploiting Write-Back Buffer
Transient execution attacks are critical security threats since those attacks exploit speculative execution which is an essential …
Jongmin Lee
,
Junyeon Lee
,
Taeweon Suh
,
Gunjae Koo
PDF
Code
Project
Slides
Video
DOI
Slide Show
Stealth ECC: A Data-Width Aware Adaptive ECC Scheme for DRAM Error Resilience
As DRAM process technology scales down and DRAM density continues to grow, DRAM errors have become a primary concern in modern data …
Young Seo Lee
,
Gunjae Koo
,
Young-Ho Gong
,
Sung Woo Chung
PDF
Project
Slides
Video
DOI
Slide Show
Restore Buffer Overflow Attacks: Breaking Undo-Based Defense Schemes
Transient execution attacks have been severe security threats since such attacks exploit architectural vulnerabilities in out-of-order …
Jongmin Lee
,
Gunjae Koo
PDF
Cite
Code
Project
Slides
Video
DOI
Slide Show
GraphSSD: Graph Semantics Aware SSD
Graph analytics play a key role in a number of applications such as social networks, drug discovery, and recommendation systems. Given …
Kiran Kumar Matam
,
Gunjae Koo
,
Haipeng Zha
,
Hung-Wei Tseng
,
Murali Annavaram
PDF
Cite
Project
DOI
Custom Link
Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs
Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To …
Yunho Oh
,
Gunjae Koo
,
Murali Annavaram
,
Won Woo Ro
PDF
Cite
Project
DOI
Custom Link
CTA-Aware Prefetching and Scheduling for GPU
Albeit GPUs are supposed to be tolerant to long latency of data fetch operation, we observe that L1 cache misses occur in a bursty …
Gunjae Koo
,
Hyeran Jeon
,
Zhenhong Liu
,
Nam Sung Kim
,
Murali Annavaram
PDF
Cite
Project
Slides
DOI
Slide Show
Summarizer: Trading Communication with Computing near Storage
Modern data center solid state drives (SSDs) integrate multiple general-purpose embedded cores to manage flash translation layer, …
Gunjae Koo
,
Kiran Kumar Matam
,
Te I
,
H. V. Krishna Giri Narra
,
Jing Li
,
Hung-Wei Tseng
,
Steven Swanson
,
Murali Annavaram
PDF
Cite
Project
Poster
Slides
DOI
Slide Show
Access Pattern-Aware Cache Management for Improving Data Utilization in GPU
Long latency of memory operation is a prominent performance bottleneck in graphics processing units (GPUs). The small data cache that …
Gunjae Koo
,
Yunho Oh
,
Won Woo Ro
,
Murali Annavaram
PDF
Cite
Project
Slides
DOI
Slide Show
Warped-Preexecution: A GPU Pre-Execution Approach for Improving Latency Hiding
This paper presents a pre-execution approach for improving GPU performance, called P-mode (pre-execution mode). GPUs utilize a number …
Keunsoo Kim
,
Sangpil Lee
,
Myung Kuk Yoon
,
Gunjae Koo
,
Won Woo Ro
,
Murali Annavaram
PDF
Cite
Project
DOI
Custom Link
»
Cite
×