Register File

Conflict-Aware Compiler for Hierarchical Register File on GPUs
Modern graphics processing units (GPUs) leverage a high degree of thread-level parallelism, necessitating large-sized register files …
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Conflict-Aware Compiler for Hierarchical Register File on GPUs
Hi-End: Hierarchical, Endurance-Aware STT-MRAM-Based Register File for Energy-Efficient GPUs
Modern Graphics Processing Units (GPUs) require large hardware resources for massive parallel thread executions. In particular, modern …
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Hi-End: Hierarchical, Endurance-Aware STT-MRAM-Based Register File for Energy-Efficient GPUs
Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs
Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To …
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Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs
Improving Energy Efficiency of GPUs through Data Compression and Compressed Execution
GPU design trends show that the register file size will continue to increase to enable even more thread level parallelism. As a result …
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Warped-Compression: Enabling Power Efficient GPUs through Register Compression
This paper presents Warped-Compression, a warp-level register compression scheme for reducing GPU power consumption. This work is …
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