One paper accepted to Journal of Systems Architecture (Journal, SCIE)

One paper has been accepted to Journal of Systems Architecture. Our paper presents SparsePIM+, an HBM-based PIM architecture for accelerating SpMV kernels using logic-die accmulation. SpasrePIM+ is an extended research work from SparsePIM presented at ICS 2025. SparsePIM+ implements the accumulator logic on the logic die of an HBM stack to further merge the partial sums created on PIM dies. SparsePIM implements an efficient dataflow to the logic-die accumulators by issuing partial results opportunistically through underutilized TSVs.