Accepted

One paper accepted to IEEE CAL (Journal, SCIE)
A paper on a PIM architecture for accelerating GeMV-softmax computation has been accepted for publication in IEEE Computer Architecture Letters. (Congrats Taewoon!)
Jul 18, 2026 1 min read Journal
One paper accepted to IEEE CAL (Journal, SCIE)
Two papers accepted to MICRO 2026
Our paper on an entry merge scheme for UVM of GPU was accepted to MICRO 2026. (Congrats Jane and Sejin!) Another paper on an efficient Tensor Core architecture for CGEMM was also accepted. (Congrats Eunbi!)
Jul 8, 2026 1 min read Conference
Two papers accepted to MICRO 2026
One paper accepted to Journal of Systems Architecture (Journal, SCIE)
A paper on an HBM-based PIM architecture for SpMV using logid-die accumulation has been accepted to Journal of Systems Architecture. (Congrats Taewoon!)
Jun 15, 2026 1 min read Journal
One paper accepted to Journal of Systems Architecture (Journal, SCIE)
One paper accepted to IEEE Access (Journal, SCIE)
A paper on an efficient kernel design approach for large-scale GNNs has been accepted for publication in IEEE Access. (Congrats Inje and Jihun!)
Jun 12, 2026 1 min read Journal
One paper accepted to IEEE Access (Journal, SCIE)
One paper accepted to Euro-Par 2026
Our paper on characterization of LLM inferences on Tenstorrent AI accelerators was accepted to ISPASS 2025. (Congrats Jangho!)
May 1, 2026 1 min read Conference
One paper accepted to Euro-Par 2026
Two papers accepted to ICS 2026
A paper on an HBM-based PIM architecture for sumcheck-based ZKPs has been accepted to ICS 2026. (Congrats Sunchae and Taewoon!). Another paper on an accelerator architecture for ternary LLMs has been accepted also (Congrats Wonseok and Junseok!).
Apr 4, 2026 1 min read Conference
Two papers accepted to ICS 2026
One paper accepted to IEEE Micro (Journal, SCIE)
A paper on an accelerator architecture on logarithmic number systems was accepted to IEEE Micro. (Congrats Yujin!)
Feb 11, 2026 1 min read Journal
One paper accepted to IEEE Micro (Journal, SCIE)
One paper accepted to IISWC 2025
Our paper on hybrid systolic array architecture fo CVNNs was accepted to IISWC 2025. (Congrats Ji Yeong and Eunbi!)
Aug 13, 2025 1 min read Conference
One paper accepted to IISWC 2025
One paper accepted to ICCD 2025
Our paper on a neural network accelerator exploiting factorized input features was accepted to ICCD 2025. (Congrats Yujin and Chanhun!)
Aug 1, 2025 1 min read Conference
One paper accepted to ICCD 2025
One paper accepted to LCTES 2025
Our paper on an efficient FFT kernel for embedded GPUs was accepted to LCTES 2025. (Congrats Dongwon!)
Apr 22, 2025 1 min read Conference
One paper accepted to LCTES 2025