Scheduling

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs
Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To …
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Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs
CTA-Aware Prefetching and Scheduling for GPU
Albeit GPUs are supposed to be tolerant to long latency of data fetch operation, we observe that L1 cache misses occur in a bursty …
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CTA-Aware Prefetching and Scheduling for GPU
Warped-Preexecution: A GPU Pre-Execution Approach for Improving Latency Hiding
This paper presents a pre-execution approach for improving GPU performance, called P-mode (pre-execution mode). GPUs utilize a number …
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Revealing Critical Loads and Hidden Data Locality in GPGPU Applications
In graphics processing units (GPUs), memory access latency is one of the most critical performance hurdles. Several warp schedulers and …
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