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LogFlex: Flexible-Bit Log Arithmetic Accelerator for Language Models on Edge
Deploying language models (LMs) on resource-constrained mobile/wearable devices while maintaining the output quality is challenging. To …
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LogFlex: Flexible-Bit Log Arithmetic Accelerator for Language Models on Edge
TM-Training: An Energy-Efficient Tiered Memory System for Deep Learning Training in NPUs
DRAM accounts for a large fraction of the total cost of ownership of memory systems in deep learning acceleration systems. To achieve …
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TM-Training: An Energy-Efficient Tiered Memory System for Deep Learning Training in NPUs
MOST: Memory Oversubscription-Aware Scheduling for Tensor Migration on GPU Unified Storage
Deep Neural Network (DNN) training demands large memory capacities that exceed the limits of current GPU onboard memory. Expanding GPU …
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MOST: Memory Oversubscription-Aware Scheduling for Tensor Migration on GPU Unified Storage
Beyond VABlock: Improving Transformer Workloads through Aggressive Prefetching
The memory capacity constraint of GPUs is a major challenge in running large deep learning workloads with their ever increasing memory …
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Beyond VABlock: Improving Transformer Workloads through Aggressive Prefetching
TLP Balancer: Predictive Thread Allocation for Multitenant Inference in Embedded GPUs
This letter introduces a novel software technique to optimize thread allocation for merged and fused kernels in multitenant inference …
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TLP Balancer: Predictive Thread Allocation for Multitenant Inference in Embedded GPUs
SAVector: Vectored Systolic Arrays
Conventional DNN inference accelerators are designed with a few (up to four) large systolic arrays. As such a scale-up architecture …
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SAVector: Vectored Systolic Arrays
Conflict-Aware Compiler for Hierarchical Register File on GPUs
Modern graphics processing units (GPUs) leverage a high degree of thread-level parallelism, necessitating large-sized register files …
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Conflict-Aware Compiler for Hierarchical Register File on GPUs
Adaptive Kernel Merge and Fusion for Multi-Tenant Inference in Embedded GPUs
This paper proposes a new scheme that improves throughput and reduces queuing delay while running multiple inferences in embedded …
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Adaptive Kernel Merge and Fusion for Multi-Tenant Inference in Embedded GPUs
Vizard: Passing over Profiling-Based Detection by Manipulating Performance Counters
Cache side-channel attacks have been serious security threats to server computer systems, thus researchers have proposed software-based …
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Vizard: Passing over Profiling-Based Detection by Manipulating Performance Counters
Analyzing GCN Aggregation on GPU
Graph convolutional neural networks (GCNs) are emerging neural networks for graph structures that include large features associated …
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Analyzing GCN Aggregation on GPU