Taeweon Suh

Latest

• Performance Characterization and Optimization of LLM Inference on Tenstorrent AI Accelerators
• SumcheckPIM: An Efficient HBM-Based PIM Architecture for Linear Complexity Zero Knowledge Proofs
• Three Birds, One Stone: Fast, Accurate-aware and Cost-Efficient Accelerator for Ternary LLM
• SparsePIM+: Accelerating SpMV on HBM-Based PIM via Logic-Die Accumulators with Opportunistic TSV Utilization
• SparsePIM: An Efficient HBM-Based PIM Architecture for Sparse Matrix-Vector Multiplications
• Cache Side-Channel Attacks Exploiting the RISC-V Coprocessor Interface on an SoC Platform
• Cache Side-Channel Attacks Exploiting RoCC Interface on RISC-V SoC Platform
• Vizard: Passing over Profiling-Based Detection by Manipulating Performance Counters
• GhostLeg: Selective Memory Coalescing for Secure GPU Architecture
• CacheRewinder: Revoking Speculative Cache Updates Exploiting Write-Back Buffer
• Processor and Operation Thereof to Revoke Cache Memory States Utilizing Write-Back Buffer
• RT-Sniper: A Low-Overhead Defense Mechanism Pinpointing Cache Side-Channel Attacks